1. Field of the Invention
The present invention relates to a verification apparatus, a verification method, and a computer-readable recording medium for executing verification of the entirety of circuits in the case where a modification has been made to a reference circuit and a circuit to be verified.
2. Background Art
In the design step for semiconductor devices such as LSIs (hereinafter, referred to as the “semiconductor design step”), the miniaturization of circuits has been accompanied by a rise in the frequency of occurrences of ECOs (Engineering Change Order: a post-design circuit modification), and thus the importance of ECOs has increased. For example, in an ECO, a logic circuit described in the RTL (Register Transfer Level) and a netlist are modified by changing the logic thereof so as to be suitable to each other.
Since modifications are made manually in ECOs, there is a strong possibility that the designer will make an erroneous modification, and there are cases in which identifying whether an error has been made is time-consuming. Accordingly, if an error has been made, the modification error needs to be modified as well, thus lengthening the TAT (Turn Around Time).
In view of this, JP 2007-328646A (hereinafter, referred to as “Patent Document 1”) discloses technology in which, in the ECO execution step, portions in a modified HDL (Hardware Description Language) description that are different from the pre-modification logic circuit are hierarchized, and furthermore a new logic circuit is created by performing logic synthesis on the hierarchized portions, and the created logic circuit is used to replace the corresponding portion of the pre-modification logic circuit. According to the technology disclosed in Patent Document 1, the hierarchization of the differing portions enables reducing the size of the executable unit of the logic synthesis, thereby shortening the time required for again executing and confirming logic synthesis and logic equivalence verification. This consequently suppresses a lengthening of the TAT.
However, in the technology disclosed in Patent Document 1, there is the problem (the first problem) that it is not possible to deal with a case where the netlist has been manually modified due to a wiring delay, constraints in terms of the arrangement of elements, or the like. Also, in conventional ECOs, it has been necessary to execute verification for the entirety of a chip when the netlist has been manually modified, even if the pre-modification netlist and the post-modification netlist differ by only a few lines. Accordingly, there is the problem (the second problem) that designing is time-consuming, and designing cannot be made more efficient.
To solve the second problem, it is conceivable to, for example, reduce the verification range by designating a verification point with use of a verification tool. However, if such a technique is employed, another problem (the third problem) arises in that a verification omission occurs if the netlist includes a connection of which the designer is not aware.
As another example, JP H9-54787A (hereinafter, referred to as “Patent Document 2”) discloses technology in which, if a circuit parameter has been modified, portions that are influenced by the circuit parameter modification are extracted from the entirety of the circuit, and circuit simulation is executed for only the extracted portions.
According to the technology disclosed in Patent Document 2, it is possible to deal with a manual modification to the netlist as well, and thus the first problem is solved. Also, with the technology disclosed in Patent Document 2, simulation is performed only for a specified circuit, and thus the second problem is also solved. Furthermore, the portions influenced by a circuit parameter modification are automatically extracted, and therefore there is no leeway for the third problem to occur in the technology disclosed in Patent Document 2.
However, with the technology disclosed in Patent Document 2, verification is performed only for the extracted portions, and not for the entirety of the post-modification circuit, and therefore there is the problem that such technology cannot deal with a case where verification of the entirety of a circuit is necessary. For this reason, there is demand for the development of technology that shortens the design time and increases efficiency while verifying the entirety of circuits.